1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and the fabrication method, particularly to the semiconductor integrated circuit that comprises a function block and a global signal wiring, and the fabrication method.
2. Description of the Related Art
The following design techniques are generalized for high-speed, large scale integrated circuit (LSI) design. To begin with, a circuit employed in a semiconductor integrated circuit is converted into hard macro blocks (function blocks) each corresponding to a function. The function blocks are then automatically arranged upon the semiconductor integrated circuit substrate, and the terminals of each function block are electrically connected to other circuits through wiring. This type of design is executed using a computer aided design (CAD) system.
Here, the semiconductor integrated circuit includes at least an integrated circuit that employs standard cell method and an application specific integrated circuit (ASIC) or the like. A wire herein means a signal wiring having a relatively long length passing across the entire substrate, such as a data bus through which transmission/reception of a data signal is performed between function blocks or with another circuit, or an address bus through which transmission/reception of an address signal is performed. Such a signal wiring is typically called a global signal wiring. Furthermore, the substrate during the design phase means a virtual substrate constructed in a memory space of the CAD system, and corresponds to a real semiconductor substrate or a real semiconductor chip of an actual product (a semiconductor integrated circuit).
Since the number of wiring layers is limited in semiconductor integrated circuit design, when the areas above the function blocks are set as prohibition areas for the global signal wirings, the global signal wirings must bypass the function block perimeter. When the size of the function blocks is extremely large relative to the substrate size, the necessary length of the global signal wirings for bypassing is extremely long. The increased global signal wiring length may cause an operation timing error (a timing violation), requiring redesigning.
In order to avoid an increase in wiring lengths, a design method of limiting the wiring layers utilized for connecting within the function block to only a few layers from the bottom layer upward, and allocating global signal wirings to the upper wiring layers could be employed. According to this design method, the global signal wirings may pass over the function block.
However, the following problems are not taken into account in such a semiconductor integrated circuit design method.
The global signal wirings may pass over the function block with the above design method; however additional buffering cells may not be arranged inside the function block in accordance with the global signal wiring passing route. In this case, the buffering cell is a circuit (intermediate cell) that amplifies a signal (increases driving capability) to be propagated through a global signal wiring.
Furthermore, since arrangement of buffering cells within the function block is impossible, arrangement of a buffering cell outside of the function block in the vicinity of each facing side of the function block, and connecting these buffering cells by means of the global signal wiring that passes over the function block is needed. Nevertheless, in the case of a function block of a huge size, the length of the global signal wiring that passes over the function block is extremely long, and the wiring capacitance thereof increases. Even if a buffering cell of high drive ability is arranged, the signal rising/falling time falls outside of design rule limitations, and timing error occurs. That is to say, the wiring length that a buffering cell can drive has a limit. So, in the case of a function block of a huge size, since a global signal wiring that passes over the function block cannot be arranged, a global signal wiring that bypasses the function block must be arranged.
Therefore, as shown in FIG. 1, basic structure of a semiconductor integrated circuit according to a related art includes a function block 2 upon a substrate 1, a first buffering cell 3a, which is arranged in the vicinity of a first side 2a of the function block 2, a second buffering cell 3b1 and a third buffering cell 3b2, which is arranged in the vicinity of a second side 2b adjacent to the first side 2a, and a fourth buffering cell 3c, which is arranged in the vicinity of a third side 2c adjacent to the second side 2b. The first buffering cell 3a and the second buffering cell 3b1 are connected by signal wiring 4a that bypasses the function block 2. The second buffering cell 3b1 and the third buffering cell 3b2 are connected by signal wiring 4b. The third buffering cell 3b2 and the fourth buffering cell 3c are connected by signal wiring 4c that bypasses the function block 2. When global signal wiring to bypass the function block 2 is long, by reason of a limit to the wiring length that buffering cell 3a to 3c can drive, it is necessary to arrange a plurality of buffering cells between the first buffering cell 3 a and the fourth buffering cell 3c. 
It should be noted that this type of semiconductor integrated circuit design method is disclosed in U.S. Pat. No. 6,436,804 B2.